Embodiments of the invention relate generally to structures for packaging semiconductor devices and, more particularly, to a semiconductor device package structure that provides a low parasitic inductance, double-sided cooling, and easy mounting to an external circuit.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. One such power semiconductor device is a high performance, wideband gap silicon carbide (SiC) MOSFET, which has very fast switching transitions and can be used as a power or high frequency device. The SiC MOSFET is able to carry a larger amount of current and typically is able to support a larger reverse-bias voltage in the off-state than other low frequency, low power semiconductor devices, such that SiC MOSFETs are ideal for use in high end military and health care products and other cutting edge technologies.
In use, high voltage power semiconductor devices are typically surface mounted to an external circuit by way of a packaging structure, with the packaging structure providing an electrical connection to the external circuit and also providing a way to remove the heat generated by the devices and protect the devices from the external environment. Most existing packaging structures are only good for low frequency/low power applications due to limitations associated with cooling and inductance drawbacks of such packaging structures. For example, in existing packaging structures, the drain of the semiconductor device(s), such as a MOSFET for example, is connected directly to the back metal tab of the packaging structure, such that the packaging structure is considered to have a “hot tab.” Packages with hot tabs are very difficult to provide with a good thermal path in order to cool the semiconductor device(s), since one must electrically insulate the copper lands that interconnect the back side or tab of the package. Furthermore, existing packaging structures use wirebonds to make the connections from the semiconductor device to package pins, with this non-planar wirebond interconnection contributing to an increased inductance of the package. The way the pin-out of the package is configured also contributes to the overall inductance of the package due to the conduction loop that is formed when the pins are soldered to the board—with inherent spacing between the board and the package.
Accordingly there is a need for a semiconductor device package that is suitable for both high frequency and high power applications by providing low inductance interconnections and improved cooling of the semiconductor device(s). There is a further need for such a semiconductor device package to provide for easy surface mounting and attachment of the package to an external circuit while freeing the designer from having to provide voltage isolation while making high current connections to the rest of the circuit.